The present invention relates generally to integrated circuit (IC) packaging technology. More particularly, embodiments of the present invention pertain to IC packaging processes using large panel leadframes.
Leadframes are commonly used to package ICs. One example of a known leadframe IC packaging technique is shown in FIG. 1. FIG. 1 is a simplified cross-sectional view of a conventional molded leadframe package (MLP) 10. MLP 10 includes an IC die 12 attached to a die pad 14 (also referred to as a die paddle) of a leadframe by an adhesive 13. Bonding pads 18 on top of IC die 12 are connected to leads 16 of the leadframe by wirebonds 19. An encapsulant material 20 covers the package including IC die 12, wirebonds 19, and upper surfaces of die pad 14 and leads 16. Die pad 14 and leads 16 are exposed on the bottom to facilitate heat dissipation from IC die 12 and to decrease overall thickness of MLP 10. Half-etched portions 17 of the leadframe are formed on sidewall surfaces of die pad 14 and leads 16. Encapsulant material 20 extends underneath half-etched portions 17 to mechanically secure die pad 14 and leads 16 to MLP 10.
MLP 10 is typically one of many IC packages that are formed in a matrix pattern using a leadframe strip. FIG. 2 is a simplified plan view of a conventional leadframe strip 30 that can be used to form a plurality of leadframe packages. Leadframe strip 30 includes an outer frame 32 to which a number of horizontal and vertical connecting bars 36, 38 are attached. Horizontal and vertical connecting bars 36, 38 define a plurality of inner frames 40 arranged in a matrix that each include an IC receiving area (or die pad). In this example, leadframe strip 30 includes a matrix of 9×9 inner frames 40. Outer frame 32 includes a plurality of positioning holes 34 that can be used to position leadframe strip 30 on appropriate tools during die attach, wirebonding, encapsulation, and singulation processes.
FIG. 3 is an enlarged view of a portion of a leadframe strip. FIG. 3 shows the portion of leadframe strip 30 inside dashed box A of FIG. 2. FIG. 3 shows a die pad 14 and leads 16 within each inner frame 40.
There are manufacturing limitations associated with current MLP packaging techniques. For example, current MLP packaging techniques generally suffer from low productivity due to low density leadframes and/or substrates, low production rates (number of units produced per hour), high capital investments, long lead times for new tooling and qualification, and other limitations.
In light of the above and in view of a general trend of shorter produce life cycles for ICs, improved MLP packages and manufacturing methods are desired.